Flat panel display
US7923736B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2010 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Apr 13, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0225
Abstract
A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.