Electronic package having stress buffer layer on mounting surface thereof, and method for manufacturing same
US7923904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2010 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Aug 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H9/0552
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic component capable of withstanding stress from a printed circuit board or the like is provided. In an electronic component, a cavity hermetically sealed by a base and a lid is formed. In the cavity, a crystal resonator is supported by a supporting member over the top surface of the base. The base is made of glass. A stress buffer layer made of a conductive resin or the like is formed over the whole bottom surface of the base. An external electrode and an external electrode that are in continuity with the electrodes of the crystal resonator individually extend to the bottom surface of the stress buffer layer via the side surfaces of the base and stress buffer layer. The thus configured electronic component is surface-mounted by, for example, soldering the external electrode and external electrode formed on the bottom surface of the stress buffer layer to a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.