Field programmable gate array architecture having Clos network-based input interconnect
US7924052B1 · kind B1 · utility
16Cited by
33References
21Claims
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Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Jan 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cluster internal routing network for use in a programmable logic device with a cluster-based architecture employs a Clos network-based routing architecture. The routing architecture is a multi-stage blocking architecture, where the number of inputs to the first stage exceeds the number of outputs from the first stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.