Latency measurements for wireless communications
US7924054B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2010 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0682
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.