Low speed, load independent, slew rate controlled output buffer with no DC power consumption
US7924066B2 · kind B2 · utility
25Cited by
2References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2009 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.