Exact frequency translation using dual cascaded sigma-delta modulator controlled phase lock loops
US7924072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2009 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Jul 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.