Area efficient programmable read only memory (PROM) array
US7924596B2 · kind B2 · utility
1Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Feb 2, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of the array that in a standby mode shut down the entire fuse array. A fuse redundancy scheme may be used to repair a defective fuse row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.