Patent · US Active

Operation of a non-volatile memory array

US7924628B2 · kind B2 · utility

447Cited by

30References

17Claims

0Family size

Assignee

Spansion Israel Ltd · IL

Inventors

Kobi Danon · Nes Ziona, IL
Shai Eisen · Nes Ziona, IL
Marcelo Krygier · Kiryat Ono, IL

Key dates

Filing date	Nov 14, 2008
Grant date	Apr 12, 2011
Priority date	—
Expiry date	Jan 2, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2216/14
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.