Symmetry corrected high frequency digital divider
US7924966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2009 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Sep 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.