Instruction-level multithreading according to a predetermined fixed schedule in an embedded processor using zero-time context switching
US7925869B2 · kind B2 · utility
56Cited by
50References
55Claims
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Key dates
| Filing date | Dec 21, 2000 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Jun 24, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.