Hiding irrelevant facts in verification conditions
US7926037B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2006 |
| Grant date | Apr 12, 2011 |
| Priority date | — |
| Expiry date | Jun 30, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program verification process begins by converting a language of the program from a first language into an intermediate language representation. The loops of the program are eliminated. The program is converted from the intermediate language representation into a passive form. Dominators for the passive form of the program are determined. A verification condition is generated from the passive form of the program. The verification condition is structured according to the computed dominators such that when a theorem prover identifies a potential error, portions of the passive form of the program irrelevant to the potential error are ignored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.