Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits
US7927893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Feb 13, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.