Method for forming self aligned contacts for integrated circuit devices
US7928000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2007 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Oct 14, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for processing integrated circuit devices including forming self aligned contact regions. The method includes providing a partially completed semiconductor wafer, the wafer including one or more semiconductor chips, where each of the chips including a plurality of MOS gate structures. Each of the gate structures is formed on a substrate and having a first layer of silicon nitride formed overlying portions including a contact region between the gate structures. Each of the chips has conformal layer of doped silicon glass of a predetermined thickness overlying the silicon nitride layer and the gate structures. The method then applies a plasma etching process to the doped silicon glass to expose a portion of the first silicon nitride layer using an anisotropic etching component to vertically remove portions of the doped silicon glass. A step of cleaning the exposed portion of silicon nitride using an isotropic component is also included. The method forms a second silicon nitride layer on the exposed portion of the second silicon nitride layer and removes the second silicon nitride layer and exposed portion of the first silicon nitride layer to expose the contract region on th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.