Electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components

US7928578B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Gianfranco Cerofolini · Milano, IT
• Danilo Mascolo · Ercolano, IT

Key dates

• Filing date: Sep 28, 2009
• Grant date: Apr 19, 2011
• Expiry date: Sep 28, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/762
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

A semiconductor electronic device that includes a semiconductor substrate having a top surface; a seed layer positioned on the substrate and having a notched wall extending transversely with respect to the substrate top surface, the wall defining a first recess extending into the seed layer with a height equal to a thickness of the seed layer; a first conductive nanowire in contact with the notched wall, the first conductive nanowire having a contact portion extending into the first recess and covering opposite sidewalls and a bottom of the first recess; a first insulating nanowire in contact with a sidewall of the first conductive nanowire; an insulating layer on the contact portion of the first conductive nanowire and having a first window substantially in correspondence with the contact portion of the first conductive nanowire; and a first conductive die on the insulating layer that includes a conductive contact extending into the first window and contacting the contact portion of the first conductive nanowire.