Tuning high-side and low-side CMOS data-paths in CML-to-CMOS signal converter
US7928765B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Aug 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electronic circuitry and techniques are disclosed for controlling one or more timing parameters associated with a circuit that converts a signal of a first type to a signal of a second type. For example, the converter circuit may convert a differential digital logic signal, such as a current mode logic (CML) signal, to a complementary metal oxide semiconductor (CMOS) signal. For example, apparatus for converting a first type of signal to a second type of signal comprises the following circuitry. First circuitry is configured for generating a first pair of CMOS signals in response to a differential digital logic signal, the first pair of CMOS signals comprising a first CMOS signal having a first polarity and a second CMOS signal having a second polarity. Second circuitry is configured for adjusting, with respect to the first pair of CMOS signals, a transition time of one of the first CMOS signal and the second CMOS signal relative to a transition time of another of the first CMOS signal and the second CMOS signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.