Patent · US Active

Efficient geometric tessellation and displacement

US7928979B2 · kind B2 · utility

11Cited by
7References
12Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 1, 2008
Grant dateApr 19, 2011
Priority date
Expiry dateJan 5, 2030

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06T2210/36
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Methods and computer-storage media are provided for rendering three-dimensional (3D) graphics by tessellating objects using novel structures and algorithms. Rendering utilizing “patches,” configurable functions that include a specified number of control points, allows for computation on a per-patch or per-control-point basis, in addition to traditional per-vertex, per-primitive, and per-pixel methods. This produces a number of advantages over previous tessellation methods, including the reuse of computations across existing vertices and the ability to process at a lower frequency. The operations to compute points are simplified in order to optimize system resources used in the process. Transitions from un-tessellated to tessellated objects are smoother utilizing the present invention, while developers have more flexibility in the level of detail present at different edges of the same patch. Detail within a displacement map also can be increased without negative effects associated with previous systems and methods.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.