Method for reducing lateral movement of charges and memory device thereof
US7929351B2 · kind B2 · utility
7Cited by
1References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2009 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Jun 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.