Interface controller that has flexible configurability and low cost
US7930462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2007 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q20/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit provides data received from a respective lane to which the SERDES circuit is coupled. A receive pipe is coupled to the SERDES circuits and comprises accumulate buffers, multiplexing levels, accumulate buffer counters, control registers, and control logic. Each accumulate buffer corresponds to a respective port configurable over the plurality of lanes. A first level of the multiplexing levels is coupled to receive data from neighboring lanes on one input and the data from the neighboring lanes connected in reverse order on the other input. Each multiplexor at each other level is coupled to receive outputs of neighboring multiplexors from a next lower level on one input and the outputs connected in reverse order on the other input. Each configuration register corresponds to a respective port, indicating an initial lane assigned to the respective port and a size of the port. The control logic is configured to generate select signals responsive to respective bits of the buffer counters and respective bits of initial lane numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.