System and method for controlling processor low power states
US7930564B2 · kind B2 · utility
13Cited by
7References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Jan 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.