Method and apparatus for reducing memory current leakage a mobile device
US7930572B2 · kind B2 · utility
3Cited by
8References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2004 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Jan 29, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.