Error rate reduction for memory arrays
US7930586B1 · kind B1 · utility
3Cited by
6References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2008 |
| Grant date | Apr 19, 2011 |
| Priority date | — |
| Expiry date | Jun 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RAID 6 system, which has two strips to hold redundant data, employs a memory array controller that at each “read” operation considers not just the data but also the redundant information, even in the absence of any indication from the collection of memory controllers associated with the hard drives that any error condition exists. Thus, with each “read” operation the array controller checks the data for an unreported error, and takes corrective action when an error condition is discovered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.