Method of manufacturing thin film transistor array substrate
US7932135B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2010 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Sep 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
Disclosed is a method of manufacturing a TFT array substrate having a reduced number of mask processes. The method includes sequentially depositing a first conductive material, a gate insulating layer, a semiconductor layer, and a second conductive material on a substrate, and forming a first resist pattern having three height levels on the second conductive material. The method further includes forming a gate line, a data line that crosses the gate line and has first and second slit units, a source electrode connected to the data line and having a third slit unit, and a drain electrode positioned opposite the source electrode with a channel interposed between the source electrode and the drain electrode and having a fourth slit unit, through a plurality of etching processes using the first resist pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.