Frequency and phase locked loop synthesizer
US7932784B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2007 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Jan 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a frequency and phase locked loop (FPLL) synthesizer having a frequency-locked loop (FLL) operating mode and a phase-locked loop (PLL) operating mode. The FLL operating mode is used for rapid coarse tuning of the FPLL synthesizer and is followed by the PLL operating mode for fine tuning and stabilization of the frequency of an output signal from the FPLL synthesizer. The FPLL synthesizer includes a variable frequency oscillator, which is controlled by FLL circuitry during the FLL operating mode or by PLL circuitry during the PLL operating mode. The FLL circuitry includes frequency division circuitry for reducing the frequency of the output signal, frequency detection circuitry for measuring the frequency error of the frequency reduced output signal, and a loop filter to control the bandwidth of an FLL control loop formed by the FLL circuitry and the variable frequency oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.