Encoding and decoding architecture and method for pipelining encoded data or pipelining with a look-ahead strategy
US7933354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2006 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2075
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An encoding and/or decoding communication system comprises a framer interface, an encoder, a multiplexer, an output driver, and a clock multiplier unit (CMU). The encoder includes an input latch circuitry stage; an output latch circuitry stage; an intermediate latch circuitry stage interposed between the input latch circuitry stage and the output latch circuitry stage, the intermediate latch circuitry stage coupled to the input latch circuitry stage and the output latch circuitry stage; a plurality of encoding logic circuitry stages interposed between the input latch circuitry stage and the output latch circuitry stage, a last one of the plurality of encoding logic circuitry stages placed adjacent to the output latch circuitry stage and coupled to the output latch circuitry stage; and a feedback between the output latch circuitry stage and the last one of the plurality of encoding logic circuitry stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.