Multiplierless FIR digital filter and method of designing the same
US7933943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2006 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0072
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a multiplierless FIR digital filter and a method of designing the same, in which a filtering operation is performed by a small addition/subtraction circuit using extracted information after analyzing the property of a given coefficient and extracting information required for design by only adding/subtracting operations. In the method of designing the multiplierless FIR digital filter, tables are created to extract and store information needed for adding and subtracting operations. An addition table is created to store values obtained by adding the input data synchronized with a clock frequency. Further, a value corresponding to multiplication is obtained by performing extraction and error correction on the added values from the tables, and an adder chain of an output terminal sums up the values and outputs the filtering results, thereby effectively implementing a logic circuit of the multipliedess FIR digital filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.