Data processing apparatus which prevents data overflow and underflow
US7933949B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2008 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Mar 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/478
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus constitutes a low-cost audio/video data transmission and reception system. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. The data processing apparatus applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.