Dynamically managing thermal levels in a processing system
US7934110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Dec 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05D23/1935
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.