Self-clearing asynchronous interrupt edge detect latching register
US7934113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2007 |
| Grant date | Apr 26, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.