Method of forming shielded gate FET with self-aligned features
US7935561B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Oct 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.