Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof
US7936002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jul 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/9202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing ste…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.