Semiconductor device having a specified terminal layout pattern
US7936071B2 · kind B2 · utility
0Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2007 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.