Leakage reduction in electronic circuits
US7936205B2 · kind B2 · utility
6Cited by
6References
60Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Jul 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.