System and method for removing nonlinearities and cancelling offset errors in comparator based/zero crossing based switched capacitor circuits
US7936291B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Oct 10, 2008 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Apr 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method compensates for errors in an output signal of a comparator based/zero crossing based circuit. The method includes generating with a comparator based/zero crossing based switched capacitor circuit a first output signal with an input signal, generating with the comparator based/zero crossing based switched capacitor circuit a second output signal with the input signal of an opposite polarity, and subtracting the second output signal from the first output signal to generate a final output signal for the comparator based/zero crossing based switched capacitor circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.