Defective bit scheme for multi-layer integrated memory device
US7936622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Nov 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.