Memory switching data processing system
US7937537B2 · kind B2 · utility
2Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2007 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Sep 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.