Methods for scalably exploiting parallelism in a parallel processing system
US7937567B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Mar 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.