Circuit and method providing dynamic scan chain partitioning
US7937634B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 17, 2009 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The circuit and method providing dynamic scan chain partitioning delivers peak power reduction by dynamically partitioning scan chains into multiple groups, wherein transitions are equally distributed among these multiple groups. For each test pattern, a particular partitioning that leads to the even partitioning of the transitions is computed by analyzing the transition distribution of the pattern. The scan chain partitioning is formulated using an Integer Linear Programming (ILP) and an efficient greedy heuristic. The computed information is loaded into the reconfigurable scan chain partitioning hardware during the capture window. The partitioning hardware is composed of controllable clock gating logic, which is reconfigured on a per pattern basis, wherein the reconfiguration is effected by only utilizing the existing scan channels. The reconfigurability delivers a solution that is test set independent. The results confirm the superiority of dynamic scan chain partitioning over static partitioning techniques in terms of peak power reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.