Memory modules with error detection and correction
US7937641B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2006 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Mar 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory module having error detection and correction mechanisms. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal. A buffer device for a memory module. A method of operating a memory module. A memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.