Error detection in physical interfaces for point-to-point communications between integrated circuits
US7937644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2010 |
| Grant date | May 3, 2011 |
| Priority date | — |
| Expiry date | Feb 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0092
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.