Multilayer chip scale package
US7939940B2 · kind B2 · utility
1Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Feb 23, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resin coated copper foil is used to fabricate a multilayer Chip Scale Package (CSP). A CSP package base has a first electrical routing layer. A resin coated copper foil is hot pressed onto the CSP package base and then patterned to form a second electrical routing layer. Conductive vias are then formed between the electrical routing layers. An Organic Solder Preservative (OSP) is used a surface finish for solder balls of the CSP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.