Edge rate control for I2C bus applications
US7940102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2010 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Apr 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/166
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.