Automatic load balancing of a 3D graphics pipeline
US7940261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2007 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.