Unlock mode in source synchronous receivers
US7940878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2007 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.