Array of processing elements with local registers

US7941634B2 · kind B2 · utility

Assignee

• Thomson Licensing · FR

Inventors

• Marco Georgi · Langenhagen, DE
• Klaus Gaedke · Hannover, DE
• Malte Borsum · Hannover, DE

Key dates

• Filing date: Nov 14, 2007
• Grant date: May 10, 2011
• Expiry date: May 30, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/8023
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Specialized image processing circuitry is usually implemented in hardware in a massively parallel way as a single instruction multiple data (SIMD) architecture. The invention prevents long and complicated connection paths between a processing element and the memory subsystem, and improves maximum operating frequency. An optimized architecture for image processing has processing elements that are arranged in a two-dimensional structure, and each processing element has a local storage containing a plurality of reference pixels that are not neighbors in the reference image. Instead, the reference pixels belong to different blocks of the reference image, which may vary for different encoding schemes. Each processing element has a plurality of local first registers for holding the reference image data: one of the first registers holds reference input data of a first search block, and some of the remaining first registers holding reference input data of further search blocks that have specified positions relative to the first search block.