Jump instruction having a reference to a pointer for accessing a branch address table
US7941653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2008 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processor, the first jump instruction referencing a pointer to a first target address in the memory table, the processor executing the first jump instruction by jumping to the first target address and modifying the pointer to point to a second target address in the memory table, the second target address corresponding to a second jump instruction. The execution of the first jump instruction may include prefetching at least one future target address from the memory table and writing the future target address in a local memory. The second target address may be accessed in the local memory in response to detection of the second jump instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.