Method of IC design optimization via creation of design-specific cells from post-layout patterns
US7941776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2007 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Feb 16, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A closed-loop IC design optimization process by automatically or manually creating design-specific cells with desired characteristics (e.g., performance, area, power, noise, etc.), which will be then implemented as a standard cell (also known hereafter as metacell), from a set of post-layout patterns. A post-layout pattern represents a part or whole of a standard cell and contains information regarding the pattern including, but not limited to, layout, timing, area, power and noise. As the metacells are created from post-layout patterns, the inaccuracies of prior dynamic library techniques are easily avoided. Such metacells, being design-specific, are optimized to satisfy the constraints imposed by the design context, thus bringing the powerful design-specific customization to standard cell-based design methodology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.