On-chip test circuit and method for testing of system-on-chip (SOC) integrated circuits
US7941781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2009 |
| Grant date | May 10, 2011 |
| Priority date | — |
| Expiry date | Jun 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31724
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method of testing IP cores contained in a system-on-chip integrated circuit is disclosed. An operation command is received on an input/output port of the circuit. The operation command includes an operation code component, data component(s), and expected time component. The received operation command is processed to supply test data to each of the IP cores being tested. Result data is received in response to the supplied test data from each of the IP cores being tested. The result data is processed and from the processed result data is generated a status data packet. The status data packet includes the operation code component and a status flag component and is provided on the input/output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.