Reproducible, high yield method for fabricating ultra-short T-gates on HFETs
US7943286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Oct 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0272
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.