Structure for a memory switching data processing system
US7945740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Mar 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.