Clock generation for multiple clock domains
US7945803B2 · kind B2 · utility
9Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2006 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Jun 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.